Espressif Systems /ESP32-C6 /SPI0 /SPI_MEM_AXI_ERR_ADDR

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Interpret as SPI_MEM_AXI_ERR_ADDR

Description

SPI0 AXI request error address.

Fields

SPI_MEM_AXI_ERR_ADDR	This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
SPI_MEM_ALL_FIFO_EMPTY	The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.
SPI_RDATA_AFIFO_REMPTY	1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
SPI_RADDR_AFIFO_REMPTY	1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
SPI_WDATA_AFIFO_REMPTY	1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
SPI_WBLEN_AFIFO_REMPTY	1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
SPI_ALL_AXI_TRANS_AFIFO_EMPTY	This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.

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